FIG. 1 shows a conventional Field Programmable Gate Array (FPGA) 1 having an array of configurable logic blocks (CLBs) 2 surrounded by input/output blocks (IOBs) 3. The CLBs 2 are individually programmable and can be configured to perform a variety of logic functions ranging from simple AND gates to more complex functions of a few input signals. A programmable interconnect structure 4 includes a matrix of programmable switches (PSMs) 5 which can be programmed to selectively route signals between the various CLBs 2 and IOBs 3 and thus produce more complex functions of many input signals. The IOBs 3 can be configured to drive output signals from the CLBs 2 to external pins (not shown) of FPGA 1 and/or to receive input signals from the external FPGA pins.
The CLBs 2, IOBs 3, and PSMs 5 of FPGA 1 are programmed by loading configuration data into memory cells (not shown for simplicity) connected to CLBs 2, IOBs 3, and PSMs 5. These memory cells control various switches and multiplexers within respective CLBs 2, IOBs 3, and PSMs 5 which implement logic and routing functions specified by the configuration data in the memory cells. Configuration data is provided to FPGA 1 via a configuration port 6 and thereafter routed to the memory cells using a dedicated configuration structure (not shown here but described in U.S. Pat. Nos. Re34,363, 5,430,687, 5,742,531, and 5,844,829). Configuration port 6 is connected to the dedicated configuration structure by a configuration access port (CAP) 7, which is essentially a bus access point. Further information regarding various types of FPGAs can be found in "The Programmable Logic Data Book 1998", published in 1998 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Configuration data is typically downloaded to an FPGA from a host system such as a personal computer or workstation using an FPGA interface cable, as illustrated in FIG. 2. Well known design tool software operating on a suitable microprocessor within host system 20 creates a configuration bitstream which embodies the logic functions desired to be implemented by the target FPGA. The configuration bitstream is downloaded from host system 20 to interface cable 15 using, for instance, a serial port or a USB port. The interface cable 15 preferably includes an on-board FPGA that customizes the configuration bitstream received from the host system 20 into a format usable by target FPGA 10, although in some embodiments host system 20's microprocessor is used to customize the configuration bitstream for target FPGA 10. Since an FPGA is able to customize configuration data at a rate much faster than that of a microprocessor, FPGA interface cables having an on-board FPGA provide superior performance.
Typically, the voltage levels used to represent logic high for signals on the interface cable must be substantially equal to that of logic signals on the target device to ensure compatibility. For instance, where the interface cable utilizes 3.3 volt logic and the target device utilizes 2.5 volt logic, driving the target device with the logic signals provided by the interface device may damage the target device. Accordingly, as improvements in silicon processing technology allow for target devices having smaller and smaller voltage levels, the voltage levels of associated interface cables must be updated accordingly in order to maintain compatibility. The required compatibility of logic signals between interface cables and target devices undesirably shortens the useful life of interface cables each time a lower voltage level is used on the target devices. Accordingly, it would be desirable to ensure an interface cable's compatibility with the target device without having to modify internal logic signals used by the interface cable.